The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs, but it has also increased the complexity of processing and manufacturing ICs.
For example, a spacer technique is generally used for doubling the exposed patterns when fabricating fin field effect transistor (FinFET) devices. That is, the pitch of a final pattern is reduced to only half compared with the first exposed pattern. A typical spacer technique uses two masks. The first one defines a mandrel pattern in a first exposure and the second one defines a cut pattern in a second exposure. The cut pattern removes unwanted portions of the mandrel pattern, a derivative, or both. Subsequently, spacer patterns are formed on sidewalls of the remaining mandrel patterns. The pitch of the spacer patterns is reduced to only half compared with the pitch of the mandrel patterns. The spacer patterns are used for patterning layers in or on a semiconductor substrate, for example, in the process of forming gate electrodes for FinFETs.
As device integration increases, it is frequently desirable to pack multiple blocks or macros into one IC chip and further place them abutted in layout in order to save wafer area. These blocks or macros have their own pattern pitches, which may vary from block to block. These abutting blocks or macros may include logic blocks, SRAM (Static Random Access Memory) blocks, and other macros. The patterns in these abutting blocks may be formed using the spacer technique discussed above. However, it remains challenging how to effectively and efficiently design the mandrel patterns for these abutting blocks as the mandrel patterns need to accommodate different pattern pitches when crossing block boundaries.